Field of the Invention
The present invention is related to semiconductor manufacturing and particularly to precisely and efficiently etching semiconductor manufacturing layers.
Background Description
Primary integrated circuit (IC) chip manufacturing goals include increasing chip density and performance at minimized power consumption, i.e., packing more function operating at higher speeds in the same or smaller space. Transistors or devices are formed by stacking layers of shapes on the IC, e.g., printed layer by layer on a wafer using photolithographic techniques. A simple field effect transistor (FET), or device, includes a gate above a semiconductor channel, a dielectric gate sidewall spacer, e.g., nitride, over source/drain extensions at each end of the channel, and source/drain regions outboard of the gate sidewall spacers. Shrinking/reducing chip layer thicknesses and feature sizes to increase density and performance provides a corresponding reduction in minimum device dimensions and spacing.
However, shrinking features and reducing thicknesses requires more precise process control for state of the art and newer IC fabrication. RIE has worked well for typical semiconductor manufacturing processes, but it is too coarse for much finer features and much thinner layer in leading edge technologies. Atomic Layer Etching (ALE) offers atomic scale precision and better-control than RIE. Unfortunately, because of the different nature ALE, RIE control approaches have not transferred to ALE.
ALE uses a sequence alternating between self-limiting chemical modification and etching. For example, chlorine reacting with a silicon surface may alternate with etching in argon ions in an argon plasma etch. The chemical modification steps only alter specific areas of the top atomic layers of the wafer being etched. The etching steps remove only the chemically-modified material from those area. With adequate control ALE provides for precisely removing individual atomic layers, but process control has not previously been addressed and commercial ALE use has been plagued with throughput problems.
Thus, there is a need for precise and efficient Atomic Layer Etch (ALE) controls in semiconductor manufacturing and more particularly for monitoring ALE to precisely determine when the etch is complete without over-etching or unintentionally etching previously formed layers or features.